DC-DC flyback converters are well known. When isolation between the input and output stage is required, the output voltage can be sensed by various methods for providing feedback. One way to convey the output voltage to the primary side while maintaining isolation is to use an optocoupler. However, using an optocoupler requires additional circuitry, space, power, and cost. A more elegant way of detecting the output voltage is to sense a voltage at a terminal of the power switch when the power switch is turned off during the discharge (or flyback) cycle of the converter. Such a sensed voltage is related in a known manner to the output voltage.
FIG. 1 illustrates one type of flyback converter which detects the output voltage VOUT by detecting the voltage at the primary winding L1 of the transformer T1 when the power switch MOSFET MPOWER is turned off during the discharge (or flyback) cycle. Sensing an output voltage by a signal at the primary side of a transformer is sometimes referred to as primary side sensing.
The MOSFET MPOWER is controlled by an output regulation and control circuit 14 to connect the primary winding L1 between the input voltage VIN (e.g., a battery voltage) and ground during a charging cycle.
To achieve a regulated VOUT, the MOSFET MPOWER is turned off after a controlled time, and the Schottky diode D becomes forward biased. A conventional pn diode may also be used. The current through the secondary winding L2 is transferred to the load and the smoothing capacitor COUT at the required voltage.
For regulation feedback, the circuit 14 detects the voltage at the drain of MOSFET MPOWER during the discharge cycle (MOSFET MPOWER is off). The drain voltage is related to the winding ratio of L1 and L2, and the voltage across winding L2 is the output voltage Vout plus the voltage drop across the diode D. Such primary side sensing circuits for detecting VOUT are well known and need not be described in detail. The full data sheet for the Linear Technology LT3573 flyback converter, incorporated herein by reference and available on-line, describes the operation of the feedback circuit. This operation is also described in U.S. Pat. Nos. 7,471,522 and 7,463,497, assigned to the present assignee and incorporated herein by reference. Other known primary side voltage sensing techniques may be used.
The circuit 14 continues to control the duty cycle of the MOSFET MPOWER, at a variable frequency or a fixed frequency, to regulate VOUT based on the sensed voltage.
The output regulation and control circuit 14 may use any type of conventional technique to regulate, including current mode, voltage mode, or other modes.
In the example of FIG. 1, a voltage mode converter is shown. During a time when the MOSFET MPOWER is off and when the diode D is conducting current, the switch voltage VSW at the drain of the MOSFET MPOWER is sensed by an output voltage sense circuit 16. The circuit 16 includes a circuit that subtracts VIN from VSW (to obtain the voltage across the winding L1) then scales the voltage to generate a feedback voltage VFB, wherein, when VFB equals a reference voltage VREF, the output voltage VOUT is at the desired value, such as 5 volts. The circuit 16 generates VFB in accordance with the following equation:
      V    FB    =            (                        V          OUT                +                              V            F                    ⁡                      (            T            )                              )        ·                  N        P                    N        S              ·    Kp  
where VF(T) is the forward voltage drop of diode D, NP/NS is the turns ratio of L1 and L2, and Kp is a proportion defined by a resistor divider. The voltage drop across the diode D has a negative temperature coefficient and is about −2 mV/K. Since the converter adjusts the duty cycle of MOSFET MPOWER to keep VFB equal to VREF, the output voltage VOUT becomes higher than the desired voltage as the temperature rises.
At some point during the discharge phase, VFB is sampled by a sample and hold circuit 18, and the sampled VFB is applied to one input of an error amplifier 20. The error amplifier 20 compares VFB to a reference voltage VREF and outputs an error voltage VE. A pulse generator 22 sets the duty cycle of the MOSFET MPOWER to cause the error voltage VE to approximately equal zero. In this way the output voltage VOUT is regulated, albeit temperature dependent. The pulse generator 22 may include a current source that charges a capacitor based the value of VE to create a threshold voltage, a ramp generator, a PWM comparator that compares the threshold voltage to the ramp for setting the duty cycle, and drive circuitry for the MOSFET MPOWER. Such circuitry is conventional.
FIG. 2 illustrates the current through the primary winding L1, the current through the secondary winding L2, and the voltage VSW across the MOSFET MPOWER for a particular duty cycle.
At time T1, the MOSFET MPOWER turns on to charge the primary winding L1, causing a ramping current to flow in winding L1. The diode D is not conducting at this time.
After a variable or fixed time, at time T2, MOSFET MPOWER shuts off and the diode D conducts. This ceases current in the primary winding L1 and causes the current through the secondary winding L2 to ramp down while charging the output capacitor COUT and providing current to the load. The voltage across the MOSFET MPOWER is related to the output voltage VOUT and is sampled during this time by the circuit 14.
At time T3, the secondary winding L2 current ramps down to zero and the diode D stops conducting to cause a discontinuous mode. For higher current loads, there may be no discontinuous operation while the duty cycle varies to regulate the output voltage.
After time T3, the parasitic capacitance of MOSFET MPOWER and the inductance of winding L1 create an oscillating tank circuit.
At time T4, MOSFET MPOWER turns on again, and the cycle repeats.
Additional detail of various converter circuits are described in U.S. Pat. Nos. 5,481,178; 6,127,815; 6,304,066; and 6,307,356, assigned to the present assignee and incorporated herein by reference.
FIG. 3 illustrates a conventional isolated flyback converter where the primary side sensing is implemented with a third winding L3, having NB turns, also referred to as a bias winding. During the discharge phase, a voltage will be generated across the third winding L3. The circuit formed of capacitor CBIAS and diode DBIAS limits spikes. The voltage VB is sensed by the output voltage sense circuit and scaled to generate the feedback voltage VFB in accordance with the following equation, previously described.
      V    FB    =            (                        V          OUT                +                              V            F                    ⁡                      (            T            )                              )        ·                  N        B                    N        S              ·    Kp  
FIG. 4 illustrates a prior art circuit within the output voltage sense circuit 16 of FIG. 1 that subtracts the VIN voltage from the VSW voltage and scales down the voltage with resistors RP1 and RP2. The VFB voltage can be expressed as
      V    FB    =            (                        V          OUT                +                              V            F                    ⁡                      (            T            )                              )        ·                  N        P                    N        S              ·                  R                  P          ⁢                                          ⁢          1                            R                  P          ⁢                                          ⁢          2                    
In FIG. 4, current source 24 draws a current through the p-channel MOSFET M1, having its source connected to VIN. The p-channel MOSFETs M1 and M2 have their gates connected so that the source of MOSFET M2 is at VIN, assuming equal threshold voltages. This subtracts VIN from VSW. Since the converter adjusts the duty cycle to keep VFB matched to VREF, the current through the resistor RP2 must be controlled, by adjusting VSW, to produce VREF. The user selects the resistor RP1 needed to scale VFB to generate the desired output voltage and connects the resistor RP1 to a terminal of the package housing the converter control circuit 14. RP2 may be 10K ohms and formed on the same chip as the converter control circuit 14.
FIG. 5 illustrates a prior art circuit within the output voltage sense circuit 16 of FIG. 3 that scales down the voltage VB with resistors RB1 and RB2. The VFB voltage can be expressed as
      V    FB    =            (                        V          OUT                +                              V            F                    ⁡                      (            T            )                              )        ·                  N        B                    N        S              ·                  R                  B          ⁢                                          ⁢          2                                      R                      B            ⁢                                                  ⁢            1                          +                  R                      B            ⁢                                                  ⁢            2                              
Since VF(T) in the various equations varies with temperature, and VOUT is directly set by VFB, VOUT slopes upward with temperature, as shown in FIG. 6. Thus, VOUT has a positive temperature coefficient. When the various components are set at room temperature, VOUT is only accurate at room temperature. In some environments, VOUT varies as much as 300 mV during the operation of the converter due to temperature changes. This is very significant when the nominal VOUT is 5 V or 3.3 V.
It is known to add a temperature-dependent offset voltage to VFB to compensate for the change in VF(T) of the diode D.
FIGS. 7 and 8 illustrate prior art temperature compensation circuits added to the circuits of FIGS. 4 and 5, respectively. A conventional bandgap voltage generator provides a stable reference voltage VREF to the base of the bipolar transistor 28. The VBE of the transistor 28 has a negative temperature coefficient of about −2 mV/K. The voltage at the emitter of the transistor 28 is across the temperature compensation resistor RTC, which is an external (off-chip) resistor selected by the user. The current through the transistor 28 and through the MOSFET M4 is thus set by the value of RTC and the changing VBE with temperature. MOSFET M3 is connected as a current mirror and adds a variable current ITC to the VFB node. The negative temperature coefficient of VF(T) is offset by the positive temperature coefficient of the current ITC.
The main problem with the temperature compensation circuits of FIGS. 7 and 8 is that the user first selects RP1 to generate the desired VOUT at room temperature, then the user heats up the converter to determine the slope of VOUT vs. temperature. Then the user selects RTC to offset the VOUT slope (i.e., makes it independent of temperature). However, since the ITC current is always applied as a bias current to the VFB node, the selection of RTC changes VFB, even at room temperature, requiring the user to select a different RP1 to achieve the desired VOUT. This results in the need to tweak RTC again. The more iterations performed, the more optimal the selection of RP1 and RTC. This is a tedious process that still results in non-optimized RP1 and RTC values. Once the user has settled on RP1 and RTC values, the user may set the final circuit design for production.
What is needed is a temperature compensation technique for an isolated flyback converter, using primary side sensing and an output diode, which does not require an iterative process for selecting an optimal value scaling resistor for VOUT and an optimal value temperature compensation resistor for compensating VOUT.